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ICCS
2005
Springer
14 years 28 days ago
A Logarithmic Time Method for Two's Complementation
This paper proposes an innovative algorithm to find the two’s complement of a binary number. The proposed method works in logarithmic time (O(logN)) instead of the worst case li...
Jung-Yup Kang, Jean-Luc Gaudiot
ITC
1999
IEEE
78views Hardware» more  ITC 1999»
13 years 11 months ago
Minimized power consumption for scan-based BIST
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
Stefan Gerstendörfer, Hans-Joachim Wunderlich
IJCAI
1993
13 years 8 months ago
Nonmonotonic Model Inference-A Formalization of Student Modeling
A student model description language and its synthesis method are presented. The language called SMDL is based on a logic programming language taking 4 truth values such as true, ...
Mitsuru Ikeda, Yasuyuki Kono, Riichiro Mizoguchi
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
13 years 5 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
EVOW
2001
Springer
13 years 12 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...