Sciweavers

564 search results - page 85 / 113
» Wireplanning in logic synthesis
Sort
View
IPSN
2010
Springer
14 years 2 months ago
Distributed genetic evolution in WSN
Wireless Sensor Actuator Networks (WSANs) extend wireless sensor networks through actuation capability. Designing robust logic for WSANs however is challenging since nodes can aï¬...
Philip Valencia, Peter Lindsay, Raja Jurdak
GECCO
2005
Springer
196views Optimization» more  GECCO 2005»
14 years 28 days ago
Providing information from the environment for growing electronic circuits through polymorphic gates
This paper deals with the evolutionary design of programs (constructors) that are able to create (n+2)-input circuits from n-input circuits. The growing circuits are composed of p...
Michal Bidlo, Lukás Sekanina
ASAP
2007
IEEE
123views Hardware» more  ASAP 2007»
13 years 9 months ago
Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors
FPGA (Field Programmable Gate Array) based reconfigurable processor has been shown to meet the increasingly challenging performance targets and shorter time-to-market pressures. I...
Siew Kei Lam, Thambipillai Srikanthan
FPGA
2008
ACM
142views FPGA» more  FPGA 2008»
13 years 9 months ago
Modeling routing demand for early-stage FPGA architecture development
Architecture development for FPGAs has typically been a very empirical discipline, requiring the synthesis of benchmark circuits into candidate architectures. This is difficult to...
Wei Mark Fang, Jonathan Rose
ASE
2010
129views more  ASE 2010»
13 years 7 months ago
Efficient monitoring of parametric context-free patterns
Recent developments in runtime verification and monitoring show that parametric regular and temporal logic specifications can be efficiently monitored against large programs. Howev...
Patrick O'Neil Meredith, Dongyun Jin, Feng Chen, G...