564 search results - page 90 / 113 » Wireplanning in logic synthesis |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alte...
GECCO
2009
Springer
14 years 1 months ago
2009
Springer
We propose a crossover operator that works with genetic programming trees and is approximately geometric crossover in the semantic space. By defining semantic as program’s eval...
RV
2009
Springer
14 years 1 months ago
2009
Springer
Synthesizing monitor circuits for LTL formulas is expensive, because the number of flip-flops in the circuit is exponential in the length of the formula. As a result, the IEEE st...
IOLTS
2008
IEEE
14 years 1 months ago
2008
IEEE
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
AHS
2007
IEEE
14 years 1 months ago
2007
IEEE
System-on-Chip devices containing both conventional and reconfigurable circuits are increasing in popularity. However the on-chip debug support infrastructure required to aid syst...