564 search results - page 91 / 113 » Wireplanning in logic synthesis |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Scheduling is an important step in high-level synthesis (HLS). In our tool, we perform scheduling in two steps: coarse-grain scheduling, in which we take into account the whole co...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
We propose a novel methodology to generate Application Specific Instruction Processors (ASIPs) including custom instructions. Our implementation balances performance and area req...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— Reduced ordered Binary Decision Diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synt...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
Symmetric input identification is an important technique in logic synthesis. Previous approaches deal with this problem by building BDDs and developing algorithms to determine symm...
ACSD
2005
IEEE
14 years 1 months ago
2005
IEEE
We consider the distributed implementability problem as: Given a labeled transition system TS together with a distribution ∆ of its actions over a set of processes, does there ex...