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SLIP
2009
ACM
14 years 2 months ago
Honeycomb-structured computational interconnects and their scalable extension to spherical domains
The present paper is part of a larger effort to redesign, from the ground up, the best possible interconnect topologies for switchless multiprocessor computer systems. We focus he...
Joseph B. Cessna, Thomas R. Bewley
ISLPED
1999
ACM
131views Hardware» more  ISLPED 1999»
13 years 12 months ago
Challenges in clockgating for a low power ASIC methodology
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
David Garrett, Mircea R. Stan, Alvar Dean
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
13 years 11 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
DFT
2004
IEEE
118views VLSI» more  DFT 2004»
13 years 11 months ago
Defect Characterization for Scaling of QCA Devices
Quantum dot Cellular Automata (QCA) is amongst promising new computing scheme in the nano-scale regimes. As an emerging technology, QCA relies on radically different operations in...
Jing Huang, Mariam Momenzadeh, Mehdi Baradaran Tah...
INTEGRATION
2008
87views more  INTEGRATION 2008»
13 years 7 months ago
SafeResynth: A new technique for physical synthesis
Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design,...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco