85 search results - page 6 / 17 » Wiring edge-disjoint layouts |
ISQED
2003
IEEE
14 years 27 days ago
2003
IEEE
To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-Â...
JOIN
2007
13 years 7 months ago
2007
In VLSI layout of interconnection networks, routing two-point nets in some restricted area is one of the central operations. It aims usually to minimize the layout area, while red...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
In this paper, we introduce a new watermarking system for IP protection on post-layout design phase. Firstly the copyright is encrypted by DES (Data Encryption Standard) and then ...
DDECS
2007
IEEE
14 years 1 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...