18 search results - page 3 / 4 » Wiring layer assignments with consistent stage delays |
ICCCN
2007
IEEE
14 years 1 months ago
2007
IEEE
—Multimedia requirements of the 1990’s drove wired and optical network architects to reconsider the inefficiencies of packet switching and consider long proven methods such as...
HIPC
2000
Springer
13 years 11 months ago
2000
Springer
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...
ISCAPDCS
2004
13 years 9 months ago
2004
This paper shows that a novel network called the fat-stack is universally efficient when adequate capacity distribution is provided and is suitable for use as an interconnection n...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we address the interconnect-driven floorplanning problem that integrates OPC-friendly bus assignment with floorplanning. Buses consist of a number of horizontal/v...