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ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 9 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
AIIDE
2008
13 years 9 months ago
Offline Planning with Hierarchical Task Networks in Video Games
Artificial intelligence (AI) technology can have a dramatic impact on the quality of video games. AI planning techniques are useful in a wide range of game components, including m...
John Paul Kelly, Adi Botea, Sven Koenig
IPPS
2007
IEEE
14 years 1 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
ISORC
2005
IEEE
14 years 29 days ago
Building Responsive TMR-Based Servers in Presence of Timing Constraints
This paper is on the construction of a fault-tolerant and responsive server subsystem in an application context where the subsystem is accessed through an asynchronous network by ...
Paul D. Ezhilchelvan, Jean-Michel Hélary, M...
PADS
2003
ACM
14 years 19 days ago
HLA-based Adaptive Distributed Simulation of Wireless Mobile Systems
Wireless networks’ models differ from wired ones at least in the innovative dynamic effects of host-mobility and open-broadcast nature of the wireless medium. Topology changes d...
Luciano Bononi, Gabriele D'Angelo, Lorenzo Donatie...