Sciweavers

299 search results - page 21 / 60
» Workshop on Using Emerging Parallel Architectures for Comput...
Sort
View
CCGRID
2005
IEEE
14 years 1 months ago
Implementing a secure, service oriented accounting system for computational economies
The ability to record and account for the usage of computational resources in a standardised way across different systems from multiple administrative domains is a precursor to wi...
John D. Ainsworth, Jon MacLaren, John M. Brooke
ICS
2007
Tsinghua U.
14 years 1 months ago
Tradeoff between data-, instruction-, and thread-level parallelism in stream processors
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
Jung Ho Ahn, Mattan Erez, William J. Dally
CDES
2006
184views Hardware» more  CDES 2006»
13 years 9 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
HICSS
2006
IEEE
139views Biometrics» more  HICSS 2006»
14 years 1 months ago
Projecting Computational Sense of Self: A Study of Transition in a Chronic Illness Online Community
We report on analysis of discussions in an online community of people with chronic illness using socio-cognitively motivated, automatically produced semantic spaces. The analysis ...
Robert McArthur, Peter Bruza, Jim Warren, Debbie K...
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
14 years 2 months ago
Hardware/software co-design architecture for thermal management of chip multiprocessors
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
Omer Khan, Sandip Kundu