299 search results - page 21 / 60 » Workshop on Using Emerging Parallel Architectures for Comput... |
129
Voted
CCGRID
2005
IEEE
15 years 8 months ago
2005
IEEE
The ability to record and account for the usage of computational resources in a standardised way across different systems from multiple administrative domains is a precursor to wi...
122
Voted
ICS
2007
Tsinghua U.
15 years 9 months ago
2007
Tsinghua U.
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
152
Voted
CDES
2006
15 years 4 months ago
2006
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
94
Voted
HICSS
2006
IEEE
15 years 8 months ago
2006
IEEE
We report on analysis of discussions in an online community of people with chronic illness using socio-cognitively motivated, automatically produced semantic spaces. The analysis ...
127
Voted
DATE
2009
IEEE
15 years 9 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...