399 search results - page 21 / 80 » XTR Implementation on Reconfigurable Hardware |
CODES
2010
IEEE
13 years 5 months ago
2010
IEEE
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
ISVLSI
2006
IEEE
14 years 2 months ago
2006
IEEE
FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfig...
ARCS
2006
Springer
14 years 6 days ago
2006
Springer
We present a new concept as well as the implementation of a reconfiguration manager for a FPGA-based reconfigurable platform, the Erlangen Slot Machine (ESM). One main advantage of...
CC
2008
Springer
13 years 10 months ago
2008
Springer
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...