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AAECC
2007
Springer
111views Algorithms» more  AAECC 2007»
13 years 7 months ago
When cache blocking of sparse matrix vector multiply works and why
Abstract. We present new performance models and a new, more compact data structure for cache blocking when applied to the sparse matrixvector multiply (SpM×V) operation, y ← y +...
Rajesh Nishtala, Richard W. Vuduc, James Demmel, K...
COMCOM
2002
120views more  COMCOM 2002»
13 years 7 months ago
An interactive video delivery and caching system using video summarization
With the advance of high-speed network technologies, the availability and popularity of streaming media content over the Internet has grown rapidly in recent years. The delivery a...
Sung-Ju Lee, Wei-Ying Ma, Bo Shen
MICRO
2007
IEEE
120views Hardware» more  MICRO 2007»
14 years 2 months ago
Scavenger: A New Last Level Cache Architecture with Global Block Priority
Addresses suffering from cache misses typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, we observe that the number of inte...
Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Maina...
ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
14 years 1 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 2 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...