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ICPP
2008
IEEE
14 years 2 months ago
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
This paper presents a two-part study on managing distributed NUCA (Non-Uniform Cache Architecture) L2 caches in a future manycore processor to obtain high singlethread program per...
Lei Jin, Sangyeun Cho
WWW
2003
ACM
14 years 8 months ago
Architecture of a quality based intelligent proxy (QBIX) for MPEG-4 videos
Due to the increasing availability and use of digital video data on the Web, video caching will be an important performance factor in the future WWW. We propose an architecture of...
Peter Schojer, László Böszö...
HPCA
2006
IEEE
14 years 1 months ago
Increasing the cache efficiency by eliminating noise
Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percent...
Prateek Pujara, Aneesh Aggarwal
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
14 years 2 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
IPPS
2006
IEEE
14 years 1 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell