1000 search results - page 38 / 200 » Yield-Aware Cache Architectures |
CASES
2006
ACM
14 years 1 months ago
2006
ACM
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
DAC
2009
ACM
13 years 11 months ago
2009
ACM
Traditional debug methodologies are limited in their ability to provide debugging support for many-core parallel programming. Synchronization problems or bugs due to race conditio...
SPAA
1990
ACM
13 years 11 months ago
1990
ACM
Multithreading has been proposed as an architectural strategy for tolerating latency in multiprocessors and, through limited empirical studies, shown to offer promise. This paper ...
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
JILP
2000
13 years 7 months ago
2000
Load latency remains a signi cant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Predi...