711 search results - page 41 / 143 » Yield-aware placement optimization |
118
Voted
ICCAD
2001
IEEE
15 years 11 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
93
Voted
DAC
2006
ACM
16 years 3 months ago
2006
ACM
In a placed circuit, there are a lot of movable cells that can be flipped to further reduce the total wirelength, without affecting the original placement solution. We aim at solv...
125
Voted
MDM
2004
Springer
15 years 8 months ago
2004
Springer
Data broadcasting is well known for its excellent scalability. Multi-dimensional range queries, such as spatial range queries of geographical information for location dependent se...
120
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CDC
2009
IEEE
15 years 7 months ago
2009
IEEE
— This paper addresses the problem of localizing a source from noisy time-of-arrival measurements. In particular, we are interested in the optimal placement of M planar sensors s...
129
Voted
ICC
2007
IEEE
15 years 9 months ago
2007
IEEE
— In this paper, we address the problem of gateway placement for throughput optimization in multi-hop wireless mesh networks. Assume that each mesh nodes in the mesh network has ...