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ARC
2009
Springer
134views Hardware» more  ARC 2009»
14 years 2 months ago
A HyperTransport 3 Physical Layer Interface for FPGAs
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
Heiner Litz, Holger Fröning, Ulrich Brün...
ARC
2009
Springer
175views Hardware» more  ARC 2009»
14 years 4 months ago
A Hardware Accelerated Simulation Environment for Spiking Neural Networks
Spiking Neural Networks (SNNs) model the biological functions of the human brain enabling neuro/computer scientists to investigate how arrays of neurons can be used to solve comput...
Brendan P. Glackin, Jim Harkin, T. Martin McGinnit...
ARC
2009
Springer
142views Hardware» more  ARC 2009»
14 years 4 months ago
A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem
Abstract. This paper presents implementation results of a reconfigurable elliptic curve processor defined over prime fields GF(p). We use this processor to compare a new algorit...
Brian Baldwin, Richard Moloney, Andrew Byrne, Gary...
ARC
2009
Springer
137views Hardware» more  ARC 2009»
14 years 4 months ago
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep
This paper argues the case for the use of analytical models in FPGA architecture layout exploration. We show that the problem when simplified, is amenable to formal optimization t...
Asma Kahoul, George A. Constantinides, Alastair M....
ARC
2009
Springer
181views Hardware» more  ARC 2009»
14 years 4 months ago
CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers
Abstract. In this paper, we present CCProc, a flexible cryptography coprocessor for symmetric-key algorithms. Based on an extensive analysis of many symmetric-key ciphers, includi...
Dimitris Theodoropoulos, Alexandros Siskos, Dionis...