The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...
Son Dao Trong, Martin S. Schmookler, Eric M. Schwa...
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...
The draft revision of the IEEE Standard for FloatingPoint Arithmetic (IEEE P754) includes a definition for decimal floating-point (FP) in addition to the widely used binary FP s...
One considers the problem of finding hard to round cases of a periodic function for large floating-point inputs, more precisely when the function cannot be efficiently approxim...
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...