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ASPDAC
1995
ACM
108views Hardware» more  ASPDAC 1995»
14 years 2 months ago
Transistor reordering rules for power reduction in CMOS gates
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power cons...
Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang
ASPDAC
1995
ACM
108views Hardware» more  ASPDAC 1995»
14 years 2 months ago
Synthesis-for-testability using transformations
- We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and ...
Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
ASPDAC
1995
ACM
85views Hardware» more  ASPDAC 1995»
14 years 2 months ago
High-level synthesis scheduling and allocation using genetic algorithms
In this article a scheduling method is presented which is capable of allocating supplementary resources during scheduling. This makes it very suitable in synthesis strategies base...
Marc J. M. Heijligers, L. J. M. Cluitmans, Jochen ...
ASPDAC
1995
ACM
130views Hardware» more  ASPDAC 1995»
14 years 2 months ago
Design for testability using register-transfer level partial scan selection
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...
Akira Motohara, Sadami Takeoka, Toshinori Hosokawa...
ASPDAC
1995
ACM
104views Hardware» more  ASPDAC 1995»
14 years 2 months ago
Power analysis of a 32-bit embedded microcontroller
A new approach for power analysis of microprocessorshas recently been proposed [1]. The idea is to look at the power consumption in a microprocessor from the point of view of the ...
Vivek Tiwari, Mike Tien-Chien Lee