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ASPDAC
1999
ACM
60views Hardware» more  ASPDAC 1999»
14 years 2 months ago
Timing Optimization of Logic Network Using Gate Duplication
We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication...
Chun-hong Chen, Chi-Ying Tsui
ASPDAC
1999
ACM
80views Hardware» more  ASPDAC 1999»
14 years 2 months ago
Low Power CMOS Off-Chip Drivers with Slew-rate Difference
-- This paper proposes an approach to reduce the short circuit current of CMOS off-chip drivers by individually controlling the input slew rates 10 the P and N channel transistors ...
Rung-Bin Lin, Jinq-Chang Chen
ASPDAC
1999
ACM
100views Hardware» more  ASPDAC 1999»
14 years 2 months ago
A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition
: This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into sub...
Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Teru...
ASPDAC
1999
ACM
151views Hardware» more  ASPDAC 1999»
14 years 2 months ago
Benchmark Circuits Improve the Quality of a Standard Cell Library
-- The experience of designing and employing two benchmark circuits to improve the quality of a standard cell library is reported. It isfound that most of the errors can be uncover...
Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai
ASPDAC
1999
ACM
168views Hardware» more  ASPDAC 1999»
14 years 2 months ago
An Integrated Battery-Hardware Model for Portable Electronics
- We describe an integrated model of the hardware and the battery sub-systems in batterypowered VLSI systems. We demonstrate that, under this model and for a fixed operating voltag...
Massoud Pedram, Chi-Ying Tsui, Qing Wu