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ASPDAC
2004
ACM
83views Hardware» more  ASPDAC 2004»
14 years 3 months ago
Instruction set and functional unit synthesis for SIMD processor cores
—This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, t...
Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka,...
ASPDAC
2004
ACM
132views Hardware» more  ASPDAC 2004»
14 years 1 months ago
On handling arbitrary rectilinear shape constraint
Non-rectangular (rectilinear) shape occurs very often in deep submicron floorplanning. Most previous algorithms are designed to handle only convex rectilinear blocks. However, han...
Xiaoping Tang, Martin D. F. Wong
ASPDAC
2004
ACM
129views Hardware» more  ASPDAC 2004»
14 years 3 months ago
Instruction buffering exploration for low energy VLIWs with instruction clusters
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
Tom Vander Aa, Murali Jayapala, Francisco Barat, G...
ASPDAC
2004
ACM
87views Hardware» more  ASPDAC 2004»
14 years 3 months ago
ShatterPB: symmetry-breaking for pseudo-Boolean formulas
Many important tasks in circuit design and verification can be performed in practice via reductions to Boolean Satisfiability (SAT), making SAT a fundamental EDA problem. However ...
Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Kare...
ASPDAC
2004
ACM
104views Hardware» more  ASPDAC 2004»
14 years 3 months ago
A small-area high-performance 512-point 2-dimensional FFT single-chip processor
: A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource-saving multidatapath radix-23 computation el...
Naoto Miyamoto, Leo Karnan, Kazuyuki Maruo, Koji K...