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    A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance
    15 years 1 months ago
    A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance
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    Yu-Min Lee, Tsung-You Wu, Po-Yi Chiang
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    Correlating system test Fmax with structural test Fmax and process monitoring measurements
    15 years 1 months ago
    Correlating system test Fmax with structural test Fmax and process monitoring measurements
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    Janine Chen, Jing Zeng, Li-C. Wang, Michael Mateja
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    ASPDAC
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    Trace-based performance analysis framework for heterogeneous multicore systems
    15 years 1 months ago
    Trace-based performance analysis framework for heterogeneous multicore systems
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    Shih-Hao Hung, Chia-Heng Tu, Thean-Siew Soon
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    Obstacle-aware longest path using rectangular pattern detouring in routing grids
    15 years 1 months ago
    Obstacle-aware longest path using rectangular pattern detouring in routing grids
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    Jin-Tai Yan, Ming-Ching Jhong, Zhi-Wei Chen
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    2010
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    Minimizing clock latency range in robust clock tree synthesis
    15 years 27 days ago
    Minimizing clock latency range in robust clock tree synthesis
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    Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen
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