Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (C-Element, FIFO, and RAPPID Tag Unit), facili...
This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving As...
Shai Rotem, Ken S. Stevens, Charles Dike, Marly Ro...
We describe an extension of the virtual volume concept to multiple sensors. Data from multiple sensors are combined in real-time and mapped into a constantly updating three-dimens...