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CDES
2009
13 years 8 months ago
2009
This paper develops a delay-insensitive (DI) digital design paradigm that utilizes ternary logic as an alternative to dual-rail logic for encoding the DATA and NULL states. This ne...
CDES
2009
13 years 8 months ago
2009
Recent developments in processing devices such as graphical processing units and multi-core systems offer opportunities to make use of parallel techniques at the chip level to obt...
CDES
2007
13 years 9 months ago
2007
—Fault collapsing is the process of reducing the number of faults by using redundance and equivalence/dominance relationships among faults. Exact global fault collapsing can be e...
CDES
2007
13 years 9 months ago
2007
- Computer component fabrication is approaching physical limits of traditional photolithographic fabrication techniques. An alternative computer architecture may be enabled by the ...
CDES
2007
13 years 9 months ago
2007
- In this paper, we present a number of parallel and fault-tolerant routing schemes for a set of nanoscale spin-wave architectures. The architectures considered here have several f...