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DATE
2000
IEEE
88views Hardware» more  DATE 2000»
14 years 1 days ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
DATE
2000
IEEE
108views Hardware» more  DATE 2000»
14 years 1 days ago
A 50 Mbit/s Iterative Turbo-Decoder
Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive codin...
F. Viglione, Guido Masera, Gianluca Piccinini, Mas...
DCC
2000
IEEE
14 years 1 days ago
Arithmetic Coding for Low Power Embedded System Design
We present a novel algorithm that assigns codes to instructions during instruction code compression in order to minimize bus-related bit-toggling and thus reducing power consumpti...
Haris Lekatsas, Wayne Wolf, Jörg Henkel
ECRTS
2000
IEEE
14 years 1 days ago
Prototyping distributed multimedia systems using communicating real-time state machines
This paper describes a methodology for the development of real-time systems and shows its application to the modeling, analysis and implementation of distributed multimedia system...
Giancarlo Fortino, Libero Nigro
EUROMICRO
2000
IEEE
14 years 1 days ago
Continuous Discrete-Event Simulation of a Continuous-Media Server I/O Subsystem
When designing computer systems, simulation tools are used to imitate a real or proposed system. Complex, dynamic systems can be simulated without the cost and time constraints in...
Michael Weeks, Chris Bailey, Reza Sotudeh