Sciweavers

    11 search results - page 1 / 3
    » csreaesa 2003
    Sort
    View
    CSREAESA
    2003
    115views Embedded Systems» more  CSREAESA 2003»
    Verification Patterns for Rapid Embedded System Verification
    14 years 7 days ago
    Verification Patterns for Rapid Embedded System Verification
    Download  asusrl.eas.asu.edu
    Wei-Tek Tsai, Feng Zhu, Lian Yu, Raymond A. Paul, ...
    claim paper
    Read More »
    CSREAESA
    2003
    121views Embedded Systems» more  CSREAESA 2003»
    Design of Digital Circuits on the Basis of Hardware Templates
    14 years 7 days ago
    Design of Digital Circuits on the Basis of Hardware Templates
    Download  www.ieeta.pt
    The paper presents a technique for the design of digital circuits based on reusable hardware templates (HT). Any HT is being constructed in such a way that it might be employed for...
    Valery Sklyarov, Iouliia Skliarova
    claim paper
    Read More »
    CSREAESA
    2003
    117views Embedded Systems» more  CSREAESA 2003»
    Low-Power Dynamic Scheduling in Heterogeneous Systems
    14 years 7 days ago
    Low-Power Dynamic Scheduling in Heterogeneous Systems
    Download  www.engr.newpaltz.edu
    : This paper develops a matching and scheduling algorithm that accounts for both the execution time and the power consumption of the application. The power consumption of different...
    Saumya Uppaluri, Baback A. Izadi, Damu Radhakrishn...
    claim paper
    Read More »
    CSREAESA
    2003
    86views Embedded Systems» more  CSREAESA 2003»
    Power Optimized Combinational Logic Design
    14 years 7 days ago
    Power Optimized Combinational Logic Design
    Download  www.engr.newpaltz.edu
    In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each g...
    R. V. Menon, S. Chennupati, Naveen K. Samala, Damu...
    claim paper
    Read More »
    CSREAESA
    2003
    160views Embedded Systems» more  CSREAESA 2003»
    Worst Case Execution Time Analysis for Petri Net Models of Embedded Systems
    14 years 7 days ago
    Worst Case Execution Time Analysis for Petri Net Models of Embedded Systems
    Download  www.c-lab.de
    We present an approach for Worst-Case Execution Time (WCET) Analysis of embedded system software, that is generated from Petri net specifications. The presented approach is part ...
    Friedhelm Stappert, Carsten Rust
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.