We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
An efficient approach to full-wave impedance extraction is developed that accounts for substrate effects through the use of two-layer media Green's functions in a mixed-poten...
Covering problems arise in many areas of electronic design automation such as logic minimization and technology mapping. An exact solution can critically impact both size and perf...
Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez
We present several improvements to general-purpose sequential redundancy removal. First, we propose using a robust variety of synergistic transformation and verification algorithm...
Hari Mony, Jason Baumgartner, Viresh Paruthi, Robe...
In this paper, we present a new linear-time retiming algorithm that produces near-optimal results. Our implementation is specifically targeted at Altera's Stratix [1] FPGAbas...
Deshanand P. Singh, Valavan Manohararajah, Stephen...