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    2005
    ACM
    125views Computer Architecture» more  DAC 2005»
    Hybrid simulation for embedded software energy estimation
    13 years 9 months ago
    Hybrid simulation for embedded software energy estimation
    Download  www.cecs.uci.edu
    Software energy estimation is a critical step in the design of energyefficient embedded systems. Instruction-level simulation techniques, despite several advances, remain too slo...
    Anish Muttreja, Anand Raghunathan, Srivaths Ravi, ...
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    DAC
    2005
    ACM
    124views Computer Architecture» more  DAC 2005»
    Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
    13 years 9 months ago
    Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
    Download  www.cs.york.ac.uk
    Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
    Chong Zhao, Yi Zhao, Sujit Dey
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    DAC
    2005
    ACM
    120views Computer Architecture» more  DAC 2005»
    Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design
    14 years 8 months ago
    Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design
    Download  www.cs.ucr.edu
    In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
    Jungeun Kim, Taewhan Kim
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    DAC
    2005
    ACM
    139views Computer Architecture» more  DAC 2005»
    StressTest: an automatic approach to test generation via activity monitors
    14 years 8 months ago
    StressTest: an automatic approach to test generation via activity monitors
    Download  www.eecs.umich.edu
    The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...
    Ilya Wagner, Valeria Bertacco, Todd M. Austin
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    DAC
    2005
    ACM
    109views Computer Architecture» more  DAC 2005»
    Device and architecture co-optimization for FPGA power reduction
    14 years 8 months ago
    Device and architecture co-optimization for FPGA power reduction
    Download  www.ee.ucla.edu
    Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
    Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
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