Sciweavers

199 search results - page 15 / 40
» date 2000
Sort
View
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
13 years 11 months ago
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
Jörg Henkel, Tony Givargis, Frank Vahid
DATE
2000
IEEE
83views Hardware» more  DATE 2000»
13 years 11 months ago
Predicting Coupled Noise in RC Circuits
A novel method which can be regarded as the noisecounterpart of the celebrated Elmore’s delay formula— both being based on the first two moments of the network’s transfer fu...
Bernard N. Sheehan
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
13 years 11 months ago
A Generic Architecture for On-Chip Packet-Switched Interconnections
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
Pierre Guerrier, Alain Greiner
DATE
2000
IEEE
82views Hardware» more  DATE 2000»
13 years 11 months ago
Constructive Library-Aware Synthesis Using Symmetries
In this paper a constructive library-aware multilevel logic synthesis approach using symmetries is described. It integrates the technology-independent and technologydependent stag...
Victor N. Kravets, Karem A. Sakallah
DATE
2000
IEEE
134views Hardware» more  DATE 2000»
13 years 11 months ago
An on Chip ADC Test Structure
In this paper, a new built-in self-test structure to test the static specifications of analog to digital converters (ADCs) is presented. A ramp signal generated by an integrator ...
Yun-Che Wen, Kuen-Jong Lee