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2000
IEEE
132views Hardware» more  DATE 2000»
13 years 11 months ago
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
DATE
2000
IEEE
86views Hardware» more  DATE 2000»
13 years 11 months ago
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level
Simulation is still one of the most important subtasks when designing a VLSI circuit. However, more and more elements on a chip increase simulation runtimes. Especially on transis...
Norbert Fröhlich, Volker Gloeckel, Josef Flei...
DATE
2000
IEEE
101views Hardware» more  DATE 2000»
13 years 11 months ago
Memory Arbitration and Cache Management in Stream-Based Systems
With the ongoing advancements in VLSI technology, the performance of an embedded system is determined to a large extend by the communication of data and instructions. This results...
Françoise Harmsze, Adwin H. Timmer, Jef L. ...
DATE
2000
IEEE
85views Hardware» more  DATE 2000»
13 years 11 months ago
Meeting Delay Constraints in DSM by Minimal Repeater Insertion
We address the problem of inserting repeaters, selected from a library, at feasible locations in a placed and routed network to meet user-specified delay constraints. We use mini...
I-Min Liu, Adnan Aziz, D. F. Wong
DATE
2000
IEEE
112views Hardware» more  DATE 2000»
13 years 11 months ago
Quantitative Comparison of Power Management Algorithms
Dynamic power management saves power by shutting down idle devices. Several management algorithms have been proposed and demonstrated effective in certain applications. We quantit...
Yung-Hsiang Lu, Eui-Young Chung, Tajana Simunic, G...