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2002
IEEE
137views Hardware» more  DATE 2002»
14 years 2 months ago
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
Qin Zhao, Bart Mesman, Twan Basten
DATE
2002
IEEE
79views Hardware» more  DATE 2002»
14 years 2 months ago
Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects
This paper presents an efficient approach to compute the dominant poles for the reduced-order admittance (Y parameter) matrix of lossy interconnects. Using the global approximati...
Qinwei Xu, Pinaki Mazumder
DATE
2002
IEEE
206views Hardware» more  DATE 2002»
14 years 2 months ago
Accurate Area and Delay Estimators for FPGAs
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, P...
DATE
2002
IEEE
74views Hardware» more  DATE 2002»
14 years 2 months ago
Maze Routing with Buffer Insertion under Transition Time Constraints
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
DATE
2002
IEEE
117views Hardware» more  DATE 2002»
14 years 2 months ago
Effective Software Self-Test Methodology for Processor Cores
Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning tech...
Nektarios Kranitis, Antonis M. Paschalis, Dimitris...