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    Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design
    15 years 8 months ago
    Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design
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    Agnes Madalinski, Alexandre V. Bystrov, Victor Kho...
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    2003
    IEEE
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    A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems
    15 years 8 months ago
    A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems
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    Achim Rettberg, Mauro Cesar Zanella, Christophe Bo...
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    IEEE
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    Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling
    15 years 8 months ago
    Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling
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    Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hu...
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    Processor/Memory Co-Exploration on Multiple Abstraction Levels
    15 years 8 months ago
    Processor/Memory Co-Exploration on Multiple Abstraction Levels
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    Gunnar Braun, Andreas Wieferink, Oliver Schliebusc...
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    2003
    IEEE
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    RTL Test Pattern Generation for High Quality Loosely Deterministic BIST
    15 years 8 months ago
    RTL Test Pattern Generation for High Quality Loosely Deterministic BIST
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    Marcelino B. Santos, José M. Fernandes, Isa...
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