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DDECS
2007
IEEE
143views Hardware» more  DDECS 2007»
14 years 5 months ago
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques
Logic Soft Errors caused by radiation are a major concern when working with circuits that need to operate in harsh environments, such as space or avionics applications, where soft ...
Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Lu...
DDECS
2007
IEEE
106views Hardware» more  DDECS 2007»
14 years 5 months ago
A Proposal for ASM++ Diagrams
– Algorithmic State Machines are a 40-year old tool for the design of digital circuits. They are a good alternative to Finite State Machines, where only states can be properly de...
Santiago De Pablo, Santiago Cáceres, Jes&ua...
DDECS
2007
IEEE
139views Hardware» more  DDECS 2007»
14 years 5 months ago
Debug Patterns for Efficient High-level SystemC Debugging
This paper proposes debug patterns combined with an intuitive flow to accelerate and simplify the debugging of SystemC designs. A debug pattern provides a formalized procedure to f...
Frank Rogin, Erhard Fehlauer, Christian Haufe, Seb...
DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
14 years 5 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 5 months ago
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...