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DDECS
2009
IEEE
14 years 12 days ago
2009
IEEE
DDECS
2009
IEEE
14 years 12 days ago
2009
IEEE
DDECS
2009
IEEE
14 years 3 months ago
2009
IEEE
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....
DDECS
2009
IEEE
14 years 3 months ago
2009
IEEE
—Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. Boolean solvers wor...
DDECS
2009
IEEE
14 years 3 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...