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100
Voted
DDECS
2009
IEEE
15 years 7 months ago
2009
IEEE
127
Voted
DDECS
2009
IEEE
15 years 7 months ago
2009
IEEE
161
Voted
DDECS
2009
IEEE
15 years 10 months ago
2009
IEEE
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....
129
Voted
DDECS
2009
IEEE
15 years 10 months ago
2009
IEEE
—Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. Boolean solvers wor...
127
Voted
DDECS
2009
IEEE
15 years 10 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...