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DFT
2003
IEEE
246views VLSI» more  DFT 2003»
13 years 12 months ago
Low Cost Convolutional Code Based Concurrent Error Detection in FSMs
We discuss the use of convolutional codes to perform concurrent error detection (CED) in finite state machines (FSMs). We examine a previously proposed methodology, we identify i...
Konstantinos Rokas, Yiorgos Makris, Dimitris Gizop...
DFT
2003
IEEE
98views VLSI» more  DFT 2003»
13 years 12 months ago
Constrained ATPG for Broadside Transition Testing
In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally...
Xiao Liu, Michael S. Hsiao
DFT
2003
IEEE
79views VLSI» more  DFT 2003»
13 years 12 months ago
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits
A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic cir...
Kartik Mohanram, Nur A. Touba
DFT
2003
IEEE
86views VLSI» more  DFT 2003»
13 years 12 months ago
CROWNE: Current Ratio Outliers with Neighbor Estimator
Increased leakage and process variations make distinction between fault-free and faulty chips by IDDQ test difficult. Earlier the concept of Current Ratios (CR) was proposed to sc...
Sagar S. Sabade, D. M. H. Walker
DFT
2003
IEEE
83views VLSI» more  DFT 2003»
13 years 12 months ago
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults
This paper proposes a new fault model and its modeling and analysis methods in a clockless asynchronous wave pipeline for extensive yield evaluation and assurance. It is highly de...
T. Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piur...