Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits

A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic circuit by targeting the error masking capability towards the nodes with the highest soft error susceptibility to achieve cost-effective tradeoffs between overhead and reduction in the soft error failure rate. Such techniques can be used in cost-sensitive high volume mainstream applications to satisfy soft error failure rate requirements at minimum cost. Two reduction heuristics, cluster sharing reduction and dominant value reduction, are used to reduce the soft error failure rate significantly with a fraction of the overhead required for conventional TMR.

• Type: Conference
• Year: 2003
• Where: DFT
• Authors: Kartik Mohanram, Nur A. Touba
• Keywords: DFT 2003, Error Failure Rate, Hardware, Soft Error, Soft Error Failure