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DFT
2005
IEEE
81views VLSI» more  DFT 2005»
14 years 1 months ago
Noise Analysis of Fault Tolerant Active Pixel Sensors
As digital imagers grow in pixel count and area, the ability to correct for pixel defects becomes more important. A fault tolerant Active Pixel Sensor (APS) has previously been de...
Cory Jung, Mohammad Hadi Izadi, Michelle L. La Hay...
DFT
2005
IEEE
92views VLSI» more  DFT 2005»
14 years 1 months ago
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lom...
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
14 years 1 months ago
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
Sandeep Kumar Goel, Erik Jan Marinissen
DFT
2005
IEEE
83views VLSI» more  DFT 2005»
14 years 1 months ago
An ILP Formulation for Yield-driven Architectural Synthesis
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
DFT
2005
IEEE
102views VLSI» more  DFT 2005»
13 years 9 months ago
Using Statistical Transformations to Improve Compression for Linear Decompressors
Linear decompressors are the dominant methodology used in commercial test data compression tools. However, they are generally not able to exploit correlations in the test data, an...
Samuel I. Ward, Chris Schattauer, Nur A. Touba