334 search results - page 15 / 67 » eXtended Block Cache |
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Combination of SECDED with a redundancy technique can effectively tolerate a high variation-induced defect rate in future processes. However, while a defective cell in a block can...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware compo...
ICCD
1999
IEEE
13 years 12 months ago
1999
IEEE
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
DSN
2011
IEEE
12 years 7 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
CODES
2003
IEEE
14 years 25 days ago
2003
IEEE
Multitasked real-time systems often employ caches to boost performance. However the unpredictable dynamic behavior of caches makes schedulability analysis of such systems difficul...