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ISCA
2012
IEEE
333views Hardware» more  ISCA 2012»
11 years 10 months ago
Reducing memory reference energy with opportunistic virtual caching
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
Arkaprava Basu, Mark D. Hill, Michael M. Swift
IEEEPACT
2007
IEEE
14 years 1 months ago
L1 Cache Filtering Through Random Selection of Memory References
Distinguishing transient blocks from frequently used blocks enables servicing references to transient blocks from a small fully-associative auxiliary cache structure. By inserting...
Yoav Etsion, Dror G. Feitelson
MICRO
2008
IEEE
174views Hardware» more  MICRO 2008»
14 years 1 months ago
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
Haiming Liu, Michael Ferdman, Jaehyuk Huh, Doug Bu...
ICCD
2000
IEEE
94views Hardware» more  ICCD 2000»
14 years 4 months ago
A Selective Temporal and Aggressive Spatial Cache System Based on Time Interval
This research proposes a new cache system that can increase the effect by temporal and spatial locality by using only simple hardware control without any locality detection hardwa...
Jung-Hoon Lee, Jang-Soo Lee, Shin-Dug Kim
ISCA
1998
IEEE
136views Hardware» more  ISCA 1998»
13 years 11 months ago
Exploiting Spatial Locality in Data Caches Using Spatial Footprints
Modern cache designs exploit spatial locality by fetching large blocks of data called cache lines on a cache miss. Subsequent references to words within the same cache line result...
Sanjeev Kumar, Christopher B. Wilkerson