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IJCAI
2003
13 years 11 months ago
Abductive Matchmaking using Description Logics
Motivated by the matchmaking problem in electronic marketplaces, we study abduction in Description Logics. We devise suitable definitions of the problem, and show how they can mod...
Tommaso Di Noia, Eugenio Di Sciascio, Francesco M....
ET
2002
72views more  ET 2002»
13 years 9 months ago
Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor
Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a prog...
Abhijit Jas, Nur A. Touba
ET
2002
67views more  ET 2002»
13 years 9 months ago
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our te...
Emmanouil Kalligeros, Xrysovalantis Kavousianos, D...
ET
2002
84views more  ET 2002»
13 years 9 months ago
Hardware Generation of Random Single Input Change Test Sequences
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
René David, Patrick Girard, Christian Landr...
ET
2002
90views more  ET 2002»
13 years 9 months ago
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...