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MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
14 years 26 days ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
MICRO
2003
IEEE
132views Hardware» more  MICRO 2003»
14 years 26 days ago
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically req...
Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasa...
MICRO
2003
IEEE
128views Hardware» more  MICRO 2003»
14 years 26 days ago
IPStash: a Power-Efficient Memory Architecture for IP-lookup
Abstract—High-speed routers often use commodity, fully-associative, TCAMs (Ternary Content Addressable Memories) to perform packet classification and routing (IP lookup). We prop...
Stefanos Kaxiras, Georgios Keramidas
MICRO
2003
IEEE
143views Hardware» more  MICRO 2003»
14 years 26 days ago
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik ...
MSS
2003
IEEE
98views Hardware» more  MSS 2003»
14 years 26 days ago
A Performance Analysis of the iSCSI Protocol
Fibre channel has long dominated the realm of storage area networks (SAN’s). However, with increased development and refining, iSCSI is fast becoming an equal contender, which ...
Stephen Aiken, Dirk Grunwald, Andrew R. Pleszkun, ...