State-of-the-art FPGAs possess I/O resources that can be configured to support a wide variety of I/O standards [1]. In such devices, the I/O resources are grouped into banks. One o...
Jason Helge Anderson, Jim Saunders, Sudip Nag, Cha...
In this paper we introduce a new Simulated Annealingbased timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a nove...
A method for evaluating and constructing sparse crossbars which are both area efficient and highly routable is presented. The evaluation method uses a network flow algorithm to ac...
It has become clear that on-chip storage is an essential component of high-density FPGAs. These arrays were originally intended to implement storage, but recent work has shown tha...
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...