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FPL
2000
Springer
122views Hardware» more  FPL 2000»
13 years 10 months ago
A Placement Algorithm for FPGA Designs with Multiple I/O Standards
State-of-the-art FPGAs possess I/O resources that can be configured to support a wide variety of I/O standards [1]. In such devices, the I/O resources are grouped into banks. One o...
Jason Helge Anderson, Jim Saunders, Sudip Nag, Cha...
FPGA
2000
ACM
119views FPGA» more  FPGA 2000»
13 years 10 months ago
Timing-driven placement for FPGAs
In this paper we introduce a new Simulated Annealingbased timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a nove...
Alexander Marquardt, Vaughn Betz, Jonathan Rose
FPGA
2000
ACM
114views FPGA» more  FPGA 2000»
13 years 10 months ago
Generating highly-routable sparse crossbars for PLDs
A method for evaluating and constructing sparse crossbars which are both area efficient and highly routable is presented. The evaluation method uses a network flow algorithm to ac...
Guy G. Lemieux, Paul Leventis, David M. Lewis
FPGA
2000
ACM
109views FPGA» more  FPGA 2000»
13 years 10 months ago
Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays
It has become clear that on-chip storage is an essential component of high-density FPGAs. These arrays were originally intended to implement storage, but recent work has shown tha...
Steven J. E. Wilton
FPGA
2000
ACM
128views FPGA» more  FPGA 2000»
13 years 10 months ago
Factoring large numbers with programmable hardware
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
Hea Joung Kim, William H. Mangione-Smith