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DATE
2005
IEEE
168views Hardware» more  DATE 2005»
14 years 3 months ago
Hardware Acceleration of Hidden Markov Model Decoding for Person Detection
This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent st...
Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
DATE
2005
IEEE
169views Hardware» more  DATE 2005»
14 years 3 months ago
Activity Packing in FPGAs for Leakage Power Reduction
In this paper, two packing algorithms for the detection of activity profiles in MTCMOS-based FPGA structures are proposed for leakage power mitigation. The first algorithm is a ...
Hassan Hassan, Mohab Anis, Antoine El Daher, Moham...
DSD
2005
IEEE
105views Hardware» more  DSD 2005»
14 years 3 months ago
Improved Fault Emulation for Synchronous Sequential Circuits
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, R...
FPT
2005
IEEE
131views Hardware» more  FPT 2005»
14 years 3 months ago
Dynamic Voltage Scaling for Commercial FPGAs
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter...
C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, ...
FPT
2005
IEEE
127views Hardware» more  FPT 2005»
14 years 3 months ago
Pipelining Saturated Accumulation
Aggressive pipelining allows FPGAs to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit pipeli...
Karl Papadantonakis, Nachiket Kapre, Stephanie Cha...