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FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
14 years 2 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk
ACST
2006
13 years 10 months ago
A combinatorial group testing method for FPGA fault location
Adaptive fault isolation methods based on discrepancyenabled pairwise comparisons are developed for reconfigurable logic devices. By observing the discrepancy characteristics of m...
Carthik A. Sharma, Ronald F. DeMara
CDES
2006
136views Hardware» more  CDES 2006»
13 years 10 months ago
CMOL FPGA circuits
Abstract--This paper describes an architecture of FPGAlike fabric for future hybrid "CMOL" circuits. Such circuits will combine a semiconductor-transistor (CMOS) stack an...
Dmitri B. Strukov, Konstantin Likharev
ARC
2006
Springer
85views Hardware» more  ARC 2006»
14 years 9 days ago
Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking
Abstract. This paper presents a hardware architecture for UNIX password cracking using Hellman's time-memory trade-off; it is the first hardware design for a key search machin...
Nele Mentens, Lejla Batina, Bart Preneel, Ingrid V...
AHS
2006
IEEE
133views Hardware» more  AHS 2006»
14 years 2 months ago
Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs
Traditional approaches to evolvable hardware (EHW), in which the field programmable gate array (FPGA) configuration is directly encoded, have not scaled well with increasing cir...
Justin Lee, Joaquin Sitte