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ERSA
2006
132views Hardware» more  ERSA 2006»
13 years 8 months ago
Combinatorial Optimization in Mapping Generalized Template Matching onto Reconfigurable Computers
: A brief review of mapping generalized template matching operations onto reconfigurable computers is given. A combinatorial optimization process, where the objective is to minimiz...
Xuejun Liang, Qutaibah M. Malluhi
JCSC
2006
73views more  JCSC 2006»
13 years 7 months ago
Architectures and FPGA Implementations of the 64-Bit MISTY1 Block Cipher
Paris Kitsos, Michalis D. Galanis, Odysseas G. Kou...
FPL
2006
Springer
158views Hardware» more  FPL 2006»
13 years 11 months ago
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. ...
Evangelia Kassapaki, Pavlos M. Mattheakis, Christo...
DAC
2006
ACM
14 years 8 months ago
A new hybrid FPGA with nanoscale clusters and CMOS routing
In this paper we propose a hybrid FPGA using nanoscale clusters with an architecture similar to clusters of traditional CMOS FPGAs. The proposed cluster is made of a crossbar of n...
Reza M. Rad, Mohammad Tehranipoor