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SIPS
2006
IEEE
14 years 2 months ago
Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
Ning Chen, Yongmei Dai, Zhiyuan Yan
ASPDAC
2006
ACM
99views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method
— This paper presents an architecture and a synthesis method for programmable numerical function generators (NFGs) for trigonometric, logarithmic, square root, and reciprocal fun...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
MOMM
2006
ACM
122views Communications» more  MOMM 2006»
14 years 2 months ago
Multimedia Tools for Teaching Reconfigurable Systems
Multimedia tools provide significant assistance in vast variety of different areas and one of them is education. The paper shows that such tools are especially important for const...
Valery Sklyarov, Iouliia Skliarova
ASAP
2006
IEEE
138views Hardware» more  ASAP 2006»
14 years 11 days ago
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
Marjan Karkooti, Predrag Radosavljevic, Joseph R. ...
ASAP
2006
IEEE
114views Hardware» more  ASAP 2006»
14 years 11 days ago
The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines
Early FPGA researchers understood that FPGAs made possible the creation of a new, flexible, and powerful class of machine -- the configurable computing machine (CCM). The earliest...
Brent E. Nelson