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CASES
2009
ACM
14 years 2 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
RECONFIG
2009
IEEE
172views VLSI» more  RECONFIG 2009»
14 years 2 months ago
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
Abstract—The main challenge when implementing cryptographic algorithms in hardware is to protect them against attacks that target directly the device. Two strategies are customar...
Shivam Bhasin, Jean-Luc Danger, Florent Flament, T...
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
14 years 2 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...
ARC
2009
Springer
241views Hardware» more  ARC 2009»
14 years 2 months ago
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm
As the need for information security increases in our everyday life, the job of encoding/decoding for secure information delivery becomes a critical issue in data network systems. ...
Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro
ARC
2009
Springer
188views Hardware» more  ARC 2009»
14 years 2 months ago
Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator
Abstract. Monte Carlo simulation is one of the most widely used techniques for computationally intensive simulations in mathematical analysis and modeling. A multivariate Gaussian ...
Chalermpol Saiprasert, Christos-Savvas Bouganis, G...