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DATE
2009
IEEE
116views Hardware» more  DATE 2009»
14 years 2 months ago
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints
In this paper, we propose a preprocessing method to improve Side Channel Attacks (SCAs) on Dual-rail with Precharge Logic (DPL) countermeasure family. The strength of our method i...
Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger,...
FCCM
2009
IEEE
164views VLSI» more  FCCM 2009»
14 years 2 months ago
A Parameterized Stereo Vision Core for FPGAs
—We present a parameterized stereo vision core suitable for a wide range of FPGA targets and stereo vision applications. By enabling easy tuning of algorithm parameters, our syst...
Stephen Longfield Jr., Mark L. Chang
ICC
2009
IEEE
145views Communications» more  ICC 2009»
14 years 2 months ago
Rapid Prototyping of Clarkson's Lattice Reduction for MIMO Detection
—This paper presents the field-programmable gate array (FPGA) implementation of a variant of the LenstraLenstra-Lov´asz (LLL) lattice reduction (LR) algorithm, known as the Cla...
Luis G. Barbero, David L. Milliner, Tharmalingam R...
RECONFIG
2009
IEEE
165views VLSI» more  RECONFIG 2009»
14 years 2 months ago
Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...
Muhammad Aqeel Wahlah, Kees G. W. Goossens
IROS
2009
IEEE
191views Robotics» more  IROS 2009»
14 years 2 months ago
Development of high-speed and real-time vision platform, H3 vision
— In this paper, we introduce a high-speed vision platform, H3 (Hiroshima Hyper Human) Vision, which can simultaneously process a 1024× 1024 pixel image at 1000 fps and a 256× ...
Idaku Ishii, Taku Taniguchi, Ryo Sukenobe, Kenichi...