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TVLSI
2010
13 years 3 months ago
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters
There is a dramatic logic density gap between FPGAs and ASICs, and this gap is the main reason FPGAs are not cost-effective in high volume applications. Modern FPGAs narrow this ga...
Peter A. Jamieson, Jonathan Rose
TC
2010
13 years 3 months ago
Reconfigurable Hardware Implementations of Tweakable Enciphering Schemes
Tweakable enciphering schemes are length preserving block cipher modes of operation that provide a strong pseudo-random permutation. It has been suggested that these schemes can b...
Cuauhtemoc Mancillas-López, Debrup Chakrabo...
ANCS
2010
ACM
13 years 6 months ago
An architecture for software defined cognitive radio
As we move forward towards the next generation of wireless protocols, the push for a better radio physical layer is ever increasing. Conventional radio architectures are limited t...
Aveek Dutta, Dola Saha, Dirk Grunwald, Douglas C. ...
INFOCOM
2010
IEEE
13 years 7 months ago
Leaping Multiple Headers in a Single Bound: Wire-Speed Parsing Using the Kangaroo System
—More fundamental than IP lookups and packet classification in routers is the extraction of fields such as IP Dest and TCP Ports that determine packet forwarding. While parsing...
Christos Kozanitis, John Huber, Sushil Singh, Geor...
CF
2010
ACM
14 years 1 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...