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FPL
2000
Springer
103views Hardware» more  FPL 2000»
14 years 2 months ago
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem
Many applications can be modeled as subgraph isomorphism problems. However, this problem is generally NP-complete and difficult to compute. A custom computing circuit is a prospect...
Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangth...
FPL
2005
Springer
100views Hardware» more  FPL 2005»
14 years 4 months ago
HAIL: A Hardware-Accelerated Algorithm for Language Identification
A hardware-accelerated algorithm has been designed to automatically identify the primary languages used in documents transferred over the Internet. The algorithm has been implemen...
Charles M. Kastner, G. Adam Covington, Andrew A. L...
FPL
2001
Springer
77views Hardware» more  FPL 2001»
14 years 3 months ago
Implementation of (Normalised) RLS Lattice on Virtex
We present an implementation of a complete RLS Lattice and Normalised RLS Lattice cores for Virtex. The cores accept 24-bit fixed point inputs and produce 24-bit fixed point predic...
Felix Albu, Jiri Kadlec, Christopher I. Softley, R...
FPL
2006
Springer
129views Hardware» more  FPL 2006»
14 years 2 months ago
A Reconfigurable Viterbi Decoder for a Communication Platform
A new large constraint length, soft decision viterbi decoder fabric is presented for deployment using platform based system on chip methodologies. The decoder can be reconfigured ...
Imran Ahmed, Tughrul Arslan
FPL
2000
Springer
93views Hardware» more  FPL 2000»
14 years 2 months ago
Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling
Abstract. Reconfigurable computing receives its merits from scheduling timebased into space-based execution. This paper reviews some common parameters and introduces an additional ...
Christian Siemers