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FPL
2004
Springer
130views Hardware» more  FPL 2004»
14 years 1 months ago
BIST Based Interconnect Fault Location for FPGAs
This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defec...
Nicola Campregher, Peter Y. K. Cheung, Milan Vasil...
FPL
2004
Springer
95views Hardware» more  FPL 2004»
14 years 1 months ago
Increasing Pipelined IP Core Utilization in Process Networks Using Exploration
At Leiden Embedded Research Center, we are building a tool chain called Compaan/Laura that allows us to do fast mapping of applications written in Matlab onto reconfigurable platf...
Claudiu Zissulescu, Bart Kienhuis, Ed F. Depretter...
FPL
2004
Springer
143views Hardware» more  FPL 2004»
13 years 11 months ago
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
Abstract. Field-Programmable Gate Arrays (FPGAs) have lately become a popular target for implementing cryptographic block ciphers, as a well-designed FPGA solution can combine some...
Joseph Zambreno, David Nguyen, Alok N. Choudhary
FPL
2004
Springer
114views Hardware» more  FPL 2004»
14 years 1 months ago
Artificial Neural Networks Processor - A Hardware Implementation Using a FPGA
Several implementations of Artificial Neural Networks have been reported in scientific papers. Nevertheless, these implementations do not allow the direct use of off-line trained n...
Pedro Ferreira, Pedro Ribeiro, Ana Antunes, Fernan...
FPL
2004
Springer
95views Hardware» more  FPL 2004»
14 years 1 months ago
Improving FPGA Performance and Area Using an Adaptive Logic Module
This paper proposes a new adaptable FPGA logic element based on fracturable 6-LUTs, which fundamentally alters the longstanding belief that a 4-LUT is the most efficient area/delay...
Michael Hutton, Jay Schleicher, David M. Lewis, Br...