This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defec...
Nicola Campregher, Peter Y. K. Cheung, Milan Vasil...
At Leiden Embedded Research Center, we are building a tool chain called Compaan/Laura that allows us to do fast mapping of applications written in Matlab onto reconfigurable platf...
Claudiu Zissulescu, Bart Kienhuis, Ed F. Depretter...
Abstract. Field-Programmable Gate Arrays (FPGAs) have lately become a popular target for implementing cryptographic block ciphers, as a well-designed FPGA solution can combine some...
Several implementations of Artificial Neural Networks have been reported in scientific papers. Nevertheless, these implementations do not allow the direct use of off-line trained n...
Pedro Ferreira, Pedro Ribeiro, Ana Antunes, Fernan...
This paper proposes a new adaptable FPGA logic element based on fracturable 6-LUTs, which fundamentally alters the longstanding belief that a 4-LUT is the most efficient area/delay...
Michael Hutton, Jay Schleicher, David M. Lewis, Br...